A large rate of current change is usually generated in the circuit of power switching devices in power electronic conversion apparatuses during the process of switching. Moreover, a relatively high voltage spike may be generated in the power switching devices due to presence of parasitic inductance, and the greater the parasitic inductance, the higher the voltage spike. Excessive voltage spike may reduce reliability of the power switching devices and increase switching losses of the power switching devices. Therefore, requirements are proposed in design of the power electronic conversion apparatuses on how to reduce the parasitic inductance in the circuit. Reduced parasitic inductance in the circuit may alleviate the voltage spike that power switching devices bear as well as allow improved efficiency by using smaller driving resistors in the power switching devices with faster switching speed and lower switching loss.
The magnitude of the parasitic inductance in the circuit is related to package and connection pattern of the power switching device. Accordingly, the parasitic inductance of the circuit is conventionally reduced by reducing a loop area including the power switching device, through inductance cancelling and the like.
FIG. 1A illustrates a circuit diagram of a two-level topology circuit in a conventional power electronic device, FIG. 1B illustrates a top view of a power conversion module corresponding to the two-level topology circuit shown in FIG. 1A, and FIG. 1C illustrates a cross sectional view of the power conversion module corresponding to the two-level topology circuit shown in FIG. 1A. As shown in FIG. 1A, in the two-level circuit, the power switching devices S1 and S2 are vertical IGBTs, which are respectively connected in anti-parallel with diodes D1 and D2. A drain of the power switching device S1 is electrically connected to an end of a capacitor C where a positive input end Vbus+ is led out. A drain of the power switching device S2 is electrically connected to a source of the power switching device S1 where an AC end is led out. A source of the power switching device S2 is electrically connected to the other end of the capacitor C where a negative input Vbus− is led out. Finally, a two-level bridge arm is thus formed. As shown in FIGS. 1B and 1C, the module includes a first substrate 4 consisting of a conductive layer 1, an insulating layer 2 and a conductive layer 3, and a second substrate 9 consisting of a conductive layer 6, an insulating layer 7 and a conductive layer 8. The conductive layer 3 is electrically connected to the conductive layer 6 via conductive material (not shown). The power switching devices S1, S2, the diodes D and D2 are arranged on the conductive layer 3, and the capacitor C is arranged on the conductive layer 8. The bonding wire 11 is configured for electrical connection between the power devices S1, S2, D1 and D2 and the capacitor C. In actual operation of the module, a first loop is formed by the power switching device S1, the diode D2 and the capacitor C, in which a direction of current flowing through the conductive layer 3 is opposite to a direction of current flowing through the conductive layer 8, so the parasitic inductance of the first loop may be reduced. Moreover, a second loop is formed by the power switching device S2, the diode D1, and the capacitor C, in which a direction of current flowing through the conductive layer 3 is opposite to a direction of current flowing through the conductive layer 8 and, likewise, the parasitic inductance of the second loop may be reduced.
However, the power conversion module has the following technical limitations.                (1) an additional second substrate 9, other than the first substrate 4, is required as the carrier plate for the capacitor C, causing an increase in cost;        (2) the difficulty of process (such as spray tin, etc.) increases, resulting in yield loss;        (3) reliability may be reduced due to multiple reflow soldering;        (4) the structure of two substrates may also increase a height of the module, and increase a size of the module, further leading to deteriorate in parasitic inductance due to the increase of pin height.        
The above-mentioned information disclosed in this section is only for the purpose of enhancing the understanding of background related to the disclosure and, thus, it may include information which does not constitute prior art known to those of ordinary skill in the art.